Conventional processes commonly used for fabricating integrated circuits having features formed in a substrate include depositing a first material layer (a “buffer layer”) into bottoms of the features and re-sputtering the material using high energy ions to facilitate redistribution from the bottoms to the sidewalls of the features. However, if the ion energy of the ions is too high, the ions may cause physical damage to the underlying layers and to the substrate itself, particularly at the corners, or bevel, and bottom of the features. Conversely, if the ion energy is too low, material may build up near the openings of the features, causing overhang build up and possibly cause the feature opening to become completely closed and form a void.
To attempt to overcome the above problems, a titanium (Ti) barrier layer may be utilized to protect the underlying substrate. However, the inventors have observed that using titanium as a barrier layer may cause the resistivity of the integrated circuit to undesirably increase. The inventors believe that this is due to the thermodynamic inter-mixing properties of the titanium layer and material layer. Alternatively, a hard mask, such as titanium nitride (TiN), may be used as a barrier layer. However, the inventors have observed that using a hard mask may induce stress within the integrated circuit, which may lead to device degradation.
Therefore, the inventors have provided improved methods for processing substrates.